1. Field of Invention
The present invention relates to the field of electrical filters. More specifically, the present invention relates to filtering or shaping circuits that convert input signals of varying amplitude to timing signals having zero crossings that do not vary in time as the input signal varies in amplitude.
2. Description of the Related Art
It is well known that time pickoff circuits are required to accurately mark the arrival time of input signals for systems utilizing time measurement. One such system is positron emission tomography (PET) where it is necessary to measure the arrival times of signals to determine when signals are in time coincidence. Fundamental to accurately marking the arrival time of input signals is the ability to reject the effects of varying single amplitude and, in some cases, varying single rise-time.
The use of simple level discriminators or comparators results in time pickoff that varies with input signal amplitude, the pickoff occurring earlier on the signal for large signals and later on the signal for smaller signals. The variation in time pickoff is known in the art as time walk. Time walk can be present for signals of varying amplitude, varying rise-time, or varying amplitude and rise-time.
A constant fraction discriminator (CFD) provides time pickoff that is insensitive to varying input signal amplitude and, in some cases, varying input signal rise-time. FIG. 1 illustrates the original CFD, a delay-line CFD 100, in which an attenuated version of the input signal is subtracted from a time-delayed version. The delay-line CFD 100 includes a delay line 102, which is a length of line which defines a particular time delay per unit length, to generate the required internal signal delay and an attenuator 104. The output of the attenuator 104 is subtracted from the output of the delay line 102 by a differencer 106. The resulting signal has a zero crossing with a fixed time relationship or delay from the start of the input signal, regardless of the amplitude for fixed-shape input signals. See D. A. Gedcke and W. J. McDonald, xe2x80x9cA Constant Fraction of Pulse Height Trigger for Optimum Time Resolution,xe2x80x9d Nucl. Instr. Meth., vol. 55, pp. 377-380, 1967.
Later, a non-delay-line CFD was reported where a single-pole, high-passed version of the input signal is subtracted from an attenuated version. See C. H. Nowlin, xe2x80x9cAmplitude- and Rise-Time-Compensated Filters,xe2x80x9d U.S. Pat. No. 4,443,768, Apr. 17, 1984; C. H. Nowlin, xe2x80x9cLow-Noise Lumped-Element Timing Filters with Rise-Time Invariant Crossover Times,xe2x80x9d Rev. Sci. Instrum., vol. 63, pp. 2322-2326, 1992. Following Nowlin, a higher-performing, non-delay-line CFD 200, illustrated in FIG. 2, was reported by the present applicant where the output of the attenuator 104 and the output of a low-pass or all-pass filter 202 are combined at the differencer 106. See D. M. Binkley, xe2x80x9cAmplitude and Rise-Time Insensitive Timing-Shaping Filters,xe2x80x9d U.S. Pat. No. 5,396,187, Mar. 7, 1995; D. M. Binkley, xe2x80x9cPerformance of Non-Delay-Line Constant-Fraction Discriminator Timing Circuits,xe2x80x9d IEEE Trans. Nucl. Sci., vol. NS 41, no. 4, pp. 1169-1175, August 1994 (describing non-delay-line CFDs in detail). The non-delay-line CFDs, while generally not providing the full performance of the delay-line CFD 100, have the substantial advantage of permitting fully monolithic integration within a single integrated circuit.
The non-delay-line CFD 200 described in U.S. Pat. No. 5,396,187 was extended when implemented in a 2-xcexcm complementary metal oxide semiconductor (CMOS) integrated circuit by the addition of gated baseline restorer (BLR) circuit. See J. M. Rochelle, D. M. Binkley, and M. J. Paulus, xe2x80x9cFully Integrated Current-Mode CMOS Gated Baseline Restorer Circuits,xe2x80x9d IEEE Trans. on Nucl. Sci., vol. 42, no. 4, pp. 729-735, August 1995. The gated BLR circuit cancels baseline dc errors associated with MOS transistor mismatches and changing input signal count rates, but does not provide the pulse tail-cancellation revealed in the present application. FIG. 3 illustrates a block diagram of the gated BLR CFD 300, which explicitly seeks to preserved the original shape by only providing correction when a signal is not present. The gated BLR CFD 300 is gated off during the presence of a signal and provides no pulse tail-cancellation. When a signal is not present, the non-delay-line, timing shaping filter output from the shaping filter 302 and the constant fraction comparator 304 is sampled by a transconductor 306. If the sampled signal is not maintained at signal ground, a voltage is developed across a capacitor 308. The capacitor voltage, in turn, causes a correction current IBLR to appear at the input of the shaping filter 302 such that the sampled signal is maintained at signal ground. The gated BLR CFD 300 explicitly seeks to preserve the original signal shape by only providing correction, or being gated on, when a signal is not present. However, conventional CFD circuits, including the gated BLR CFD 300, are not adapted to cancel the slow decay tail of the signal. The inability to cancel the pulse-tail makes conventional CFD circuits unsuitable for use in high count rate applications.
While both delay-line and non-delay-line CFDs exist in the prior art, these circuits do not permit operation for input signals operating at a high count rate. For positron emission tomography (PET) and many systems utilizing nuclear radiation detectors, the detector signal decays slowly following its arrival or leading edge. This decay characteristic is known in the art as the decay tail. If the detector signal count rate is high, it is likely new signals will occur on top of the decay tail of previous signals. The occurrence of a new signal on the decay tail of a previous signal is known in the art as pulse pileup and can create significant time pickoff errors for CFD circuits.
Although not known to be applied to CFD circuits, pulse tail-cancellation circuits for narrowing or effectively canceling the long decay tail of detector signals are known in the prior art. When the decay tail is exponential, as is frequently the case for nuclear scintillation detectors, a pole-zero network or filter can be used to cancel the pole associated with the tail decay by placing a zero at the time constant or frequency associated with the decay tail. See R. Boie, A. Hrisoho, and P. Rehak, xe2x80x9cSignal Shaping and Tail-cancellation for Gas Proportional Detectors at High Counting Rates,xe2x80x9d IEEE Trans. Nucl. Sci., vol. 28, pp. 603-609, March 1981. The pole-zero network will necessarily introduce its own pole, but the time constant associated with the decay tail frequency pole can be made shorter than the original decay tail time constant. If the pole-zero network is tuned to the decay tail of the detector pulse, the pulse tail duration can be reduced considerably. Pole-zero tail-cancellation techniques have been reported in bipolar integrated circuits. See N. Dressnandt, N. Lam, F. M. Newcomer, R. Van Berg, and H. H. Williams, xe2x80x9cImplementation of the ASDBLR Straw Tube Readout ASIC in DMILL Technology,xe2x80x9d IEEE Trans. Nucl. Sci., vol. 48, pp. 1239-1243, August 2001; B. Bevensee, F. M. Newcomer, R. Van Berg, and H. H. Williams, xe2x80x9cAn Amplifier-Shaper-Discriminator with Baseline Restoration for the ATLAS Transition Radiation Tracker,xe2x80x9d IEEE Trans. Nucl. Sci., vol. 43, pp.1725-1731, June 1996. Other pole-zero tail-cancellation techniques have been applied to CMOS integrated circuits. See A. Kandasamy, E. O""Brien, P. O""Connor, and W. Von Achen, xe2x80x9cA Monolithic Preamplifier-Shaper for Measurement of Energy Loss and Transition Radiation,xe2x80x9d IEEE Trans. Nucl. Sci., vol. 46, pp.150-155, June 1999. These techniques are designed to reduce the long ion decay tail associated with proportional chamber detectors. However, pole-zero tail-cancellation techniques have the disadvantage of requiring tuning or matching to the signal decay time constant.
If the zero of a pole-zero network or filter is placed at the origin (0 Hz or dc), the circuit reduces to a single-pole high-pass filter. Such a circuit has the advantage of reducing the signal decay tail duration while not requiring specific tuning to the decay tail characteristics. Additionally, the single-pole high-pass filter circuit simultaneously blocks dc signals, including CMOS transistor mismatch related voltages, which can result in significant time pickoff errors in practical CFD applications. A single-pole high-pass filter circuit is used in a CMOS integrated circuit for canceling the decay associated with straw tube ionization chambers. See M. J. Loinaz and B. A. Wooley, xe2x80x9cA CMOS Multichannel IC for Pulse Timing Measurements with 1-mV Sensitivity,xe2x80x9d IEEE J. Solid-State Circuits, vol. 30, pp. 1339-1349, December 1995.
However, it is not known to have pulse tail-cancellation applied directly to CFD circuits permitting accurate time pickoff of signals operating at high count rate. It is desirable to provide continual, aggressive correction in such a way as to simultaneously correct dc baseline errors and cancel the slow decay tail of the signal. This would permit operation at extremely high count rates otherwise not possible.
In summary, the original delay-line CFD, the Nowlin non-delay-line CFD, the Binkley non-delay-line CFD, and the Rochelle, et al., non-delay-line CFD with gated BLR (the Rochelle, et al. paper) all describe prior embodiments of CFD circuits but these are gated BLR""s that in no way provide pulse tail cancellation for high count rate operation. While tail-cancellation circuits exist in the prior art in fields unrelated to CFD circuits, tail-cancellation circuits have not been applied to or integrated with CFD circuits.
Accordingly, it is an object of the present invention to apply continuous-time, baseline restorer (BLR) circuits to existing CFD circuits in both the constant fraction or zero-crossing timing path and the arming path.
Another object of the present invention is that the continuous-time, BLR circuits regulate the baseline for the constant fraction or zero crossing signal and for the arming signal in CFD circuits to correct for baseline shift associated with varying input pulse count rate and device mismatch errors in integrated circuit implementations.
A further object of the present invention is that the continuous-time, BLR circuits provide simultaneous pulse-tail cancellation (providing a significant reduction in the width or duration) for the zero-crossing signal and for the arming signal in CFD circuits to permit CFD circuits to operate at very high count rates.
It is a still further object of the present invention that the continuous-time, BLR circuits provide simultaneous pulse-tail cancellation in a way where the initial portion of the zero-crossing and the arming signals is minimally affected to obtain accurate zero-crossing time discrimination and arming threshold discrimination.
A constant fraction discriminator (CFD) having built-in pulse tail-cancellation is shown and described herein. The CFD combines constant fraction shaping, arming, and baseline restoration with pulse tail-cancellation to produce a CFD capable of high count rate operation. The filter or shaping circuits described herein are insensitive to varying amplitude for arbitrary fixed-shaped input signals having a very high count rate. The CFD provides correction of dc offset and count-rate dependent baseline errors along with simultaneous tail-cancellation. Correction of dc offsets due to electronic device mismatches and count-rate dependent baseline errors is required for accurate time pickoff from the input signals. The reduction of pulse width, or pulse tail-cancellation is required to shorten the duration of high count rate signals to prevent the severe distortion caused by the occurrence a new signal superimposed on the tails of previous signals, a condition known as pulse pileup. Without pulse tail-cancellation, there are substantial errors in time pickoff due to the pulse pileup. The addition of pulse tail-cancellation permits operation of the CFD at high count rates without pulse pileup. Operation of the CFD at high count rates is significant for various applications, including positron emission tomography (PET) medical imaging scanners that utilize large area detectors.
FIG. 4 illustrates one embodiment of the CFD having built-in pulse tail-cancellation. The input to the CFD is processed in two parallel signal paths. The lower signal path contains a CF shaping filter which generates an output signal having zero crossing time that is independent of the input signal amplitude. The lower signal path includes a CF shaping filter, a CF baseline restorer (BLR) and pulse-tail-cancellation circuit, and a CF comparator. The upper signal path includes an arming BLR and pulse-tail-cancellation circuit and an arming comparator. The outputs of the CF comparator and the arming comparator are processed by the arming logic to provide a time pickoff logic signal having a fixed time relationship from the zero crossing of the signal at the input of the CF comparator. This results in time pickoff that is insensitive to varying amplitude at the CFD input.
The output of the CF shaping filter is connected to a continuous-time CF BLR tail-cancel circuit. The CF BLR tail-cancel circuit cancels dc baseline errors due to circuit offsets and baseline shift associated with varying input signal count rates. Additionally, the CF BLR tail-cancel circuit provides built-in signal decay tail-cancellation through continuous-time, wideband, negative feedback. The pulse-tail-cancellation, needed for high count-rate operation, is illustrated at the CF BLR tail-cancel circuit output. The CF BLR tail-cancel circuit holds the CF signal baseline near zero, except for the initial portion of its input signal. The CF comparator senses the zero crossing of the output of the CF BLR tail-cancel circuit providing the needed amplitude-independent time pickoff and producing a time pickoff logic output signal. Similarly, the arming BLR tail-cancel circuit cancels dc baseline errors due to circuit offsets and baseline shift associated with varying input signal count rates. Additionally, the arming BLR tail-cancel circuit provides built-in signal decay tail-cancellation through its continuous-time, wideband, negative feedback. However, unlike the CF BLR tail-cancel circuit, the arming BLR tail-cancel circuit holds the arming signal baseline below zero by an amount equal to a selected arming threshold. When the output of the arming BLR tail-cancel circuit exceeds the preset threshold, it crosses through zero and is detected by the arming comparator. The arming comparator provides an arming logic output signal.